The testing of large scale integration (LSI) packages, very large scale integration (VLSI) packages and application-specific integrated circuits (ASIC) has become increasingly important as these components and circuits continue to increase in gate densities. With every successive generation having a greater number of gates to test, simultaneous switching concerns in systems utilizing scan-based testing become more prevalent. Where every latching device in a scan chain is clocked at the same time, electrical noise caused by the simultaneous scan shifting can cause corrupted test results. Therefore, it is desirable to reduce simultaneous switch concerns in scan-based testing techniques.
Generally, scan design approaches comprise a test operation wherein certain desired logic test patterns are serially inputted and shifted to the appropriate latch locations when the unit is operated in the "shift mode" (i.e., by withholding the system clock excitations and turning on the shift scan control signals to the unit). When this is done, the latch states will provide the desired stimuli for the testing of the related logic nets. Next, the test patterns are propagated through the nets by executing one or more steps of the "function mode" operation (i.e., by exercising one or more system clock excitations). The response patterns of the logic networks to the applied stimuli is captured by the system latches, in a known manner depending on certain details of hardware design, often replacing the original inputted test patterns. Then, the system reverts to the shift-mode operation, outputting the response patterns for examination and comparison with expected patterns which should be present if the circuitry has operated properly. The scan-based test technique is employed to test the component chips of the package as well as the package. The technique logically partitions the dense scan logic into portions which are bounded on the inputs and outputs by Shift Register Latches (SRLs) and package pins wherever system logic dictates. Tests are then generated individually for each partition.
A typical scan design approach can be seen in the scan design circuit 10 of FIG. 1. Logic 12 has multiple inputs 14, and generates outputs to latch 16, and latch 18 through latch 20. Logic 22 receives inputs from latch 16, latch 18, through latch 20, and generates outputs to latch 24, latch 26 through latch 28. Logic 30 receives inputs from latch 24, latch 26 through latch 28, and has multiple outputs 32 to output the data. Each of the latching devices in circuit 10 is typically a D-type flip-flop having a data (D) input for receiving system data from the logic circuits. The scan data (SD) input of latch 16 receives logic test patterns as scan data input signals on line 34, and continually shifts its present Q output to the SD input of the next daisy-chained latch. The shift occurs each time an active pulse of the clock signal on line 36 is received at the clock (CLK) input when the scan enable (SE) input is set by the scan enable signal on line 38 to acknowledge the scan data rather than the system data. Each of the daisy-chained latches shifts its current bit to the next latch until the entire logic test pattern has been shifted in. The D inputs can then receive inputs from the logic circuits when the scan enable (SE) input is set by the scan enable signal on line 38 to acknowledge the system data rather than the scan data. The system data is then stored in parallel in the latches. The latched results of the test are then shifted out at the scan data output on line 40 to be compared to expected test pattern results.
One such scan testing system is disclosed in U.S. Pat. No. 4,817,093 issued on Mar. 28, 1989 to Jacobs et al. Jacobs et al. describes various scan test techniques, and provides a method and structure for partitioning, testing and diagnosing a multi-chip packaging structure by inhibiting all chips in the multi-chip package except for the chip or chips under test. However, Jacobs et al. only scans or tests one chip or group of chips at a time. Furthermore, such a system allows isolation of particular chips to be tested, but does not address electrical noise considerations where the chip or chips under test involves simultaneous switching of such magnitude so as to potentially corrupt the testing process. It is desirable to test all portions of one or more chips under test, while regulating the switching to avoid the adverse effects of large-scale simultaneous switching.
U.S. Pat. No. 4,644,265 issued on Feb. 17, 1987 to Davidson et al. is directed to a test system for reducing off-chip driver switching noise by implementing a sequencing network for sequentially conditioning the off-chip driver circuits for possible switching. Although Davidson et al. addresses reducing a number of driver circuits concurrently switching logic states, the system does not address noise reduction in a scan-based test system with overlapping logic clusters having the ability to perform scan shifting, releasing, and capturing operations at predetermined times. Simultaneous switching of scan-based testing systems can present immense electrical noise problems where scan chains become increasingly large.
One scan-based testing system described in U.S. Pat. No. 5,077,740 issued on Dec. 31, 1991 to Kanuma describes the testing of one or more circuit macrocells. One object of the Kanuma design is to provide a logic circuit which can separate a circuit portion to be tested from other circuit portions and test the circuit portion by using presently-available test data for the circuit portion. Another object is to provide a logic circuit which can carry out one cycle of a test while receiving data to be used for the next cycle of the test. However, such a system tests only One "portion" at a time, and a transfer clock simultaneously transfers all latched test bits in a "portion" to a shift register. Therefore, multiple portions are not concurrently tested through the use of offset clocking techniques for scan shift, release and capture functions. Similarly, U.S. Pat. No. 4,918,379 issued on Apr. 17, 1990 to Jongepier allows the testing of macro circuits, but scans or tests one section at a time.
It is therefore desirable to allow concurrent testing of multiple sections of one or more chips under scan test. The present invention provides a system and method for concurrently providing scan control signals to multiple clusters of logic to be tested, yet provides for offset scan control signalling during scan shift, release, and capture to reduce simultaneous switching. The present invention therefore provides a solution to this and other problems, and offers other advantages over the prior art.